Digital and mixed-signal ASIC/ SoC/FPGA design

Full design flow from HDL model to GDSII.

Our customers can either order a turnkey solution and let our team take care of all the design stages, or make use of one or several of our competences, including:

  • Development of technical specifications, descriptions, projects and other kinds of documents;
  • Intellectual Property (IP) core design;
  • Design of System On Chip (SoC) interconnect buses and IP core integration into a system;
  • Logical and physical synthesis;
  • Floorplanning and place-and-route;
  • Static Timing Analysis (STA), design and verification of clock domain crossing (CDC) circuits;
  • Design For Test (DFT);
  • Development of automated test programs, environments and Universal Verification Methodology (UVM) components;
  • Exhaustive ASIC/SoC/IP verification;
  • Functional verification (assertion-based, coverage-based, constraint random);
  • Formal verification;
  • Physical verification: Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC).
  • Integrated circuit testing using Automated Test Equipment (ATE): Teradyne, Form, KeySight.

IP and VIP cores

Design Center «System» has a rich ever-growing library of our own highly efficient IP-cores, including common digital peripherals, interfaces, processor cores, math and cryptographic functions. Usage of rigorously tested, silicon-proven IP cores allows us to deliver highly complex systems as quickly as possible.

The Design Center can either develop new components / IP cores for customer’s chip, or take a role of a system-level integrator by designing an appropriate interconnect bus, integrating all digital and analog blocks and performing an exhaustive testing of the system using verification IP-cores (VIP) and UVM-based test environment.


Production and shipping of integrated circuits

Design Center «System» cooperates with leading-edge chip manufacturers both in Russia and around the globe. We provide our services in communication with semiconductor foundries, ensuring that your integrated circuits are manufactured correctly and shipped on schedule, either packaged or unpackaged.

For test chips and low-volume production it is preferable to use Multi Project Wafer technology: the foundry places several chips designed by different teams on a single silicon wafer, which allows to significantly reduce mask and wafer costs. This option is often used in early stages of Research and Development for testing and post-silicon validation purposes.

Creation of a Full Mask Set (FMS) is only appropriate for high volume fabrication, as cost of such a mask set is the highest compared to other manufacturing methods. Nevertheless, it allows to minimize cost of a single chip during high-volume production.

Multi Layer Mask (MLM) technology lies in between the two aforementioned processes, which makes it ideal for medium-volume fabrication. In this technology several masks are combined into one, hence reducing the total number of masks compared to FMS creation.

Design Center «System» will, of course, provide guidance to it’s customers on manufacturing matters and help to select the optimal fabrication technology.

There are several ways we can help you bring your project to life:

  1. Design house - design an entire integrated circuit, from specification to a fully-functional device, whether it is an ASIC, SoC or an FPGA design. Carry out system-level integration: interconnect bus design, IP core integration;
  2. IP provider - design an individual IP core for your chip;
  3. Verification team - perform high quality testing, VIP development, creation of test environments, functional and formal verification
  4. ASIC designer - front-end, back-end. Carry out logical/phisical synthesis, floorplan and place-and-route an existing design;
  5. Consultant - provide expert assessment, technological and financial guidance to customers.