With more than 15 years of experience, Design Center «System» is a leading digital semiconductor design company in the Ural region. Our team has an established history of providing complex Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) solutions, all the way from from technical specification to the moment when a fully-functional chip is delivered to our customers. Our team has mastered all the stages of integrated circuit FrontEnd and BackEnd design and verification.

Sample projects

  • ASIC
    ASIC/SoC design
    • IC for digital pressure sensors. Mixed-signal. 16sq.mm. 180nm
      Ull EmbFlash TSMC, SystemVerilog. Model, synthesis, physical
      design and verification.
      • CPU 32bit, 4KiB RAM, 32KiB FLASH, PGA, current source,
        ADC (24 bit), DAC (12bit), POR, RC, SPI, UART, I2C, OWI,
        GPIO, JTAG BS + FLASH PRG
    • General purpose microcontroller. Mixed-signal. 180nm SOI
      Mikron. SystemVerilog. Model, synthesis, physical design and
      verification.
      • CPU 8bit, 256B RAM, 4KiB ROM, ADC, DAC, POR, RC,
        SPI, UART, I2C, GPIO, JTAG BS + DBG + ROM PRG
    • General purpose microcontroller. Mixed-signal. 180nm Ull
      EmbFlash TSMC, SystemVerilog. Model, synthesis, physical
      design and verification.
      • CPU 8bit, 256B RAM, 4KiB FLASH, POR, RC, USB 1.1,
        SPI, UART, I2C, GPIO
    • IC for pressure sensors. Mixed-signal. 250nm SOI Mikron.
      Verilog. Model, logical synthesis and verification.
      • CPU (8051), PGA, ADC (16 bit), DAC(10 bit), POR, SPI,
        UART, GPIO, JTAG BS.
    • A prototype of IC for medical equipment. 1sq.mm. 180nm Logic
      LV(1.5/3.3V) TSMC. SystemVerilog. Model.
      • RC, LCD driver, POR, digital filters.
    • Microcontroller 64bit. 180nm CMOS Silterra. VHDL. Model,
      logical synthesis and verification. Tests for ATE Teradyne Integra
      J750.
      • 512KiB RAM, AMBA 2.0, Ethernet 10/100 (MAC), USB 2.0
        device FS, UART, SPI, I2C, PWM, WDT, GP Timer, GPIO,
        EMI (SRAM, DRAM, PROM), DAC (10bit), ADC (4ch,
        16bit), PLL, JTAG BS + DBG, package LQFP-256.
    • Microcontroller 64bit. 180nm CMOS Silterra. VHDL. Model,
      logical synthesis and verification. Tests for ATE Teradyne Integra
      J750.
      • 128KiB RAM, AMBA 2.0, UART, SPI, I2C, PWM, WDT, GP
        Timer, GPIO, package QFP-208, CQFP-240, -60°С ... +
        125°С.
    • A sample for technology test. Digital. 100 sq.mm. 250nm SOI
      Mikron. Verilog. Model, synthesis, physical design and verification.
      Tests for ATE Form HF2.
      • 2 independent sets of logical functions with sequencers and
        logical analyzers. mil-std-1554, JTAG BS.
    • 4 digital ASIC for different purposes. 240nm SOI Mikron. Verilog.
      Model, logical synthesis and verification.
    • 15 digital ASIC for different purposes. 500nm CMOS Angstrem.
      Verilog. Model, logical synthesis and verification.
  • FPGA
    FPGA projects
    • Prototype of wireless system based on ieee 802.11ah. Verilog. Ettus B205mini-i (Xilinx Spartan-6)
    • A prototype of a system based on IEEE 802.11ah (STAs-AP). Xilinx Spartan-6 + Xilinx Kintex-7
    • System for conversion and correction (trigonometry function) an information from angle sensors. Verilog. Altera. UART, external interface for memory and I/O devices (ADC).
    • Machine vision system (video matrix I/f controller and video-signal processing blocks). Verilog. Xilinx ZYNQ. On-Semi matrix I/f, Sobel filter, AMBA AXI.
      Prototype of i/f ONFI3.2. Verilog. Xilinx Artix-7
    • Data processing systems. Xilinx Virtex UltraScale+
    • Prototypes for our ASIC/SoC projects
  • IP
    IPs and VIPs
    • IEEE 802.11ah - MAC, PLCP, PMD levels (IP and UVM VIP)
    • CAN FD – MAC, LLC levels (IP and UVM VIP)
    • ONFI3.2 NAND FLASH interface (IP and UVM VIP)
    • GOST R-3412.2015 cryptographic algorithm (IP)
    • Floating point arithmetic IPs (addition, division, multiplication, matrix multiplication, sin/cos, arctg, arcsin)
    • Mil-std-1554 (IP and UVM VIP)
    • SPI (IP and UVM VIP)
    • UART (IP and UVM VIP)
    • OWI (IP and UVM VIP)
    • I2C (IP)
    • PWM (IP)
    • CPU MC8051 (IP)
    • I2S (UVM VIP)
    • UVM RapidIO - Spec. 1.3, all types of packets, CAR/CSR for all levels (UVM VIP)
    • SpaceWire - ECSS-E-ST-50-12C, Link-Link, NULL, FCT, DATA, interleaving packets, START, AUTOSTART (UVM VIP)